The primary application of this invention is frequency synthesis and, in particular, pulse swallowing counters used in frequency synthesizers. Pulse swallowing counters of the prior art are disclosed in E.C.L. Data Book, Fairchild Camera and Instrument Corp. (Mountain View, Ca.), 1977, pages 9-56, 9-57 and 9-58.
Each of the flip-flops in such a counter is characterized by a maximum clock frequency, above which the flip-flop cannot be reliably operated. Typically, the counter must be operated substantially below this maximum clock frequency because of delays inherent in the feedback loop between the first and last flip-flops. An additional limitaton on the clock frequency is the necessity, typical with some flip-flops, of providing both a clock signal and a complementary clock signal to operate the master and slave portions, respectively, of each flip-flop. This latter limitaton arises for one of two reasons. First, if a complementary clock signal is derived from the reference clock signal by use of an inverter, the inverter itself imposes one gate delay worth of signal delay between the two clock signals, a delay which must be accommodated by a selection of a clock period one gate delay longer than would otherwise be necessary. (As used in this specification, the term "gate delay" refers to the time required for a logic change to propagate through one logic structure such as a NAND gate.) Alternatively, an independent complementary clock generator may be used, in which case the clock signal and its complement are not necessarily in phase, again imposing a delay between the two clock signals. Such a complementary clock generator is difficult to implement in some logic families such as gallium arsenide field effect transistor AND/NOR logic.
Typically, the prior art has not addressed the problems inherent in attempts to operate such dual modulus counters at the maximum clock frequency of the individual flip-flops comprising the counter. This is because the inherent delay in the feedback loop of such a counter made it impractical to run the counter at the maximum clock frequency of its flip-flops. Typically, such counters are run at frequencies significantly lower than the maximum clock frequency of the flip-flop. Thus, prior art dual modulus counters do not possess both the capability of being run at the maximum clock frequency of its individual flip-flops and the features required of such dual modulus counters. For example, one required feature in most systems is that the counter be self-initializing. That is, even though the counter may begin counting from any randomly entered state when power is first applied, it must eventually reach a counting sequence in which the desired dividing ratio is realized. Thus, the prior art has not made a counter which is both self-initializing and operable at the maximum clock rate for each flip-flop while tolerating the delay inherent in the feedback loop between the first and last flip-flops.